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# Split radix fft vhdl code thesis proposal

Publish a number of your code, and duplicateOrinsert the errors.

this is actually the code
1.FFT_primary module
library ieee
use ieee.std_logic_1164.all
use ieee.math_real.all
library work
use work.fft_pkg.all

entity fft_eightpt is
port(x:in comp_array –input over time domain
z:out comp_array) –output in frequency domain
finish fft_eightpt

architecture behav of fft_eightpt is
component butterfly is
port(x1,x2:in complex –input
w: in complex –twiddle factor
g1,g2:out complex) –output but serving as input to second and 3rd stage
finish component

signal g1,g2. comp_array := (others = (.,.))
constant w:comp_array2:=((1.,.),(.707,-.707),(.,-1.),(-.707,-.707))
begin

–first stage of butterfly mapping
buf11:butterfly port map(x(),x(4),w(),g1(),g1(1))
buf12:butterfly port map(x(2),x(6),w(),g1(2),g1(3))
buf13:butterfly port map(x(1),x(5),w(),g1(4),g1(5))
buf14:butterfly port map(x(3),x(7),w(),g1(6),g1(7))

–second stage of butterfly mapping
buf21:butterfly port map(g1(),g1(2),w(),g2(),g2(2))
buf22:butterfly port map(g1(1),g1(3),w(2),g2(1),g2(3))
buf23:butterfly port map(g1(4),g1(6),w(),g2(4),g2(6))
buf24:butterfly port map(g1(5),g1(7),w(2),g2(5),g2(7))

–3rd stage of butterfly mapping
buf31:butterfly port map(g2(),g2(4),w(),z(),z(4))
buf32:butterfly port map(g2(1),g2(5),w(1),z(1),z(5))
buf33:butterfly port map(g2(2),g2(6),w(2),z(2),z(6))
buf34:butterfly port map(g2(3),g2(7),w(3),z(3),z(7))

2.FFT_pack
library IEEE
use IEEE.std_logic_1164.all
use IEEE.MATH_REAL.ALL

package fft_pkg is

type complex is
record
r. real
i. real
finish record

type comp_array is array ( to 7) of complex
type comp_array2 is array ( to three) of complex

function add (n1,n2. complex) return complex
function sub (n1,n2. complex) return complex
function mult (n1,n2. complex) return complex

package body fft_pkg is

–inclusion of complex figures
function add (n1,n2. complex) return complex is

variable sum. complex

begin
sum.r:=n1.r + n2.r
sum.i:=n1.i + n2.i
return sum

–subtraction of complex figures.
function sub (n1,n2. complex) return complex is

variable diff. complex

begin
diff.r:=n1.r – n2.r
diff.i:=n1.i – n2.i
return diff
finish sub

–multiplication of complex figures.
function mult (n1,n2. complex) return complex is

variable prod. complex

begin
prod.r:=(n1.r * n2.r) – (n1.i * n2.i)
prod.i:=(n1.r * n2.i) + (n1.i * n2.r)
return prod
finish mult

Error:showing fatal error while running the exam bench and showing product value has run out of range.I’ve also declared one separate module for butterfly component.

Mister I’m pasting here the entire code. help me in connection with this

library ieee
use ieee.std_logic_1164.all
use ieee.math_real.all
library work
use work.fft_pkg.all

entity fft_eightpt is
port(x:in comp_array –input over time domain
z:out comp_array) –output in frequency domain
finish fft_eightpt

architecture behav of fft_eightpt is
component butterfly is
port(x1,x2:in complex –input
w: in complex –twiddle factor
g1,g2:out complex) –output but serving as input to second and 3rd stage
finish component

signal g1,g2. comp_array := (others = (.,.))
constant w:comp_array2:=((1.,.),(.707,-.707),(.,-1.),(-.707,-.707))

begin

–first stage of butterfly mapping
buf11:butterfly port map(x(),x(4),w(),g1(),g1(1))
buf12:butterfly port map(x(2),x(6),w(),g1(2),g1(3))
buf13:butterfly port map(x(1),x(5),w(),g1(4),g1(5))
buf14:butterfly port map(x(3),x(7),w(),g1(6),g1(7))

–second stage of butterfly mapping
buf21:butterfly port map(g1(),g1(2),w(),g2(),g2(2))
buf22:butterfly port map(g1(1),g1(3),w(2),g2(1),g2(3))
buf23:butterfly port map(g1(4),g1(6),w(),g2(4),g2(6))
buf24:butterfly port map(g1(5),g1(7),w(2),g2(5),g2(7))

–3rd stage of butterfly mapping
buf31:butterfly port map(g2(),g2(4),w(),z(),z(4))
buf32:butterfly port map(g2(1),g2(5),w(1),z(1),z(5))
buf33:butterfly port map(g2(2),g2(6),w(2),z(2),z(6))
buf34:butterfly port map(g2(3),g2(7),w(3),z(3),z(7))

library IEEE
use IEEE.std_logic_1164.all
use IEEE.MATH_REAL.ALL

package fft_pkg is

type complex is
record
r. real
i. real
finish record

type comp_array is array ( to 7) of complex
type comp_array2 is array ( to three) of complex

function add (n1,n2. complex) return complex
function sub (n1,n2. complex) return complex
function mult (n1,n2. complex) return complex

package body fft_pkg is

–inclusion of complex figures
function add (n1,n2. complex) return complex is

variable sum. complex

begin
sum.r:=n1.r + n2.r
sum.i:=n1.i + n2.i
return sum

–subtraction of complex figures.
function sub (n1,n2. complex) return complex is

variable diff. complex

begin
diff.r:=n1.r – n2.r
diff.i:=n1.i – n2.i
return diff
finish sub

–multiplication of complex figures.
function mult (n1,n2. complex) return complex is

variable prod. complex

begin
prod.r:=(n1.r * n2.r) – (n1.i * n2.i)
prod.i:=(n1.r * n2.i) + (n1.i * n2.r)
return prod
finish mult

library ieee
use ieee.std_logic_1164.all
library work
use work.fft_pkg.all

entity butterfly is
port(x1,x2:in complex
w:in complex
g1,g2:out complex)
finish butterfly

architecture behav of butterfly is
begin
g2= sub(x1,mult(x2,w))
finish behav

library ieee
use ieee.std_logic_1164.all
library work
use work.fft_pkg.all

entity test_bench is
finish test_bench

architecture behav of test_bench is
signal x,z:comp_array
begin
DUT:entity work.fft_eightpt port map
(x= x,
z=z)
process
begin
x() = (.5,.)
x(1) = (.5,.)
x(2) = (.5,.)
x(3) = (.5,.)
x(4) = (.,.)
x(5) = (.,.)
x(6) = (.,.)
x(7) = (.,.)
wait
finish process
finish behav

This is actually the complete code.there’s no compilation error but while simulation the exam bench(fourth module) within the code it’s saying product value has run out of range.mister help me in connection with this.

## Re: Complex muliplication and addition in VHDL radix 2 FFT project

mister still now some compilation error is originating. i’m not getting how to own default value to x.the road which u wrote
signal x. comp_array := (others = (., .) ) it’s not for x it’s for signal g1 and g2.after i am assigning any default value to x within the entity part it’s not by taking your value rather showing the mistake not suitable for work.fft_pkg. so mister how to proceed. help me

mister still now some compilation error is originating. i’m not getting how to own default value to x.the road which u wrote
signal x. comp_array := (others = (., .) ) it’s not for x it’s for signal g1 and g2.after i am assigning any default value to x within the entity part it’s not by taking your value rather showing the mistake not suitable for work.fft_pkg. so mister how to proceed. help me

## Re: Complex muliplication and addition in VHDL radix 2 FFT project

please anybody assist me to using the error what’s arriving the merchandise a part of FFT package

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