capless regulator

I’ve not attempted the design.
But, since i have also do LDO in my project, I must share my understanding about LDO. Please correct me if I am wrong. =)

Inside a three-stage LDO (i.e. two stages of error amp and something stage of pass transistor), you will find a minimum of 3 rods exist. The first is in the LDO’s output, another two are in the creation of each stage of error amp. Presuming the output cap is extremely small, which can be true because you stated about capless LDO, we are able to state that the 3 rods location is very near. To have stability, you have to:
1. push among the pole to reduce freq and push others to greater freq, or
2. additionally to step one, add LHP zero to improve the soundness much more.

There are lots of strategies to push the pole to reduce frequency. The favourite one is to apply Miller compensation, which is dependant on pole splitting technique. The issue with this particular strategy is the presence of RHP zero, that is undesirable. To get rid of this RHP zero, many method continues to be suggested, e.g. using nulling resistor, feedforward stage, current buffer, current buffer, current mirror, cascode compensation (enhanced approach to current buffer). A few of these technique even can introduce LHP zero.

Among the condition in LDO is a result of its altering load resistance. In conventional LDO, people produce a dominant pole by using this altering load resistance along with a huge output cap. The issue takes place when RL is extremely small (because of the heavy load current). At the moment, the dominant pole shifts to greater frequency, resulting in the non-dominant rods to become located within the UGF. Thus, ESR zero was utilized to pay the LDO. However, this method needs a huge cap and particular selection of ESR, making this compensation a little troubelsome and never appropriate for SoC.

Nowadays, people very seldomly utilize the output pole because the dominant one. They often produce a dominant pole using the enhanced Miller compensation, that has been previously mentioned. To pay the altering pole, many people attempt to lower the UGF and employ a continuing zero to pay it as it pertains close to the UGF. Other researchers suggested to utilize a dynamic zero, which has the capacity to change its location based on the load current. The issue with this particular strategy is that, it can’t precisely track the burden pole, since it could only track the burden current, although not the burden capacitance. However, it’s still a lot better than only a constant zero.

For that dynamic zero, you can try this paper:
– Pole-zero tracking frequency compensation for low dropout regulator
– A Minimal-dropout Regulator with Unconditional Stability and occasional Quiescent Current

I believe that’s my brief introduction about LDO. Hope it can benefit. =)
For that readers of the publish, please correct me if I am wrong.
Many thanks! =)

1 people found this publish useful.

capless regulator

I’ve not attempted the design.
But, since i have also do LDO in my project, I must share my understanding about LDO. Please correct me if I am wrong. =)

Inside a three-stage LDO (i.e. two stages of error amp and something stage of pass transistor), you will find a minimum of 3 rods exist. The first is in the LDO’s output, another two are in the creation of each stage of error amp.

Presuming the output cap is extremely small, which can be true because you stated about capless LDO, we are able to state that the 3 rods location is very near. To have stability, you have to:
1. push among the pole to reduce freq and push others to greater freq, or
2. additionally to step one, add LHP zero to improve the soundness much more.

There are lots of strategies to push the pole to reduce frequency. The favourite one is to apply Miller compensation, which is dependant on pole splitting technique. The issue with this particular strategy is the presence of RHP zero, that is undesirable. To get rid of this RHP zero, many method continues to be suggested, e.g. using nulling resistor, feedforward stage, current buffer, current buffer, current mirror, cascode compensation (enhanced approach to current buffer). A few of these technique even can introduce LHP zero.

Among the condition in LDO is a result of its altering load resistance. In conventional LDO, people produce a dominant pole by using this altering load resistance along with a huge output cap. The issue takes place when RL is extremely small (because of the heavy load current). At the moment, the dominant pole shifts to greater frequency, resulting in the non-dominant rods to become located within the UGF. Thus, ESR zero was utilized to pay the LDO. However, this method needs a huge cap and particular selection of ESR, making this compensation a little troubelsome and never appropriate for SoC.

Nowadays, people very seldomly utilize the output pole because the dominant one. They often produce a dominant pole using the enhanced Miller compensation, that has been previously mentioned. To pay the altering pole, many people attempt to lower the UGF and employ a continuing zero to pay it as it pertains close to the UGF. Other researchers suggested to utilize a dynamic zero, which has the capacity to change its location based on the load current. The issue with this particular strategy is that, it can’t precisely track the burden pole, since it could only track the burden current, although not the burden capacitance. However, it’s still a lot better than only a constant zero.

For that dynamic zero, you can try this paper:
– Pole-zero tracking frequency compensation for low dropout regulator
– A Minimal-dropout Regulator with Unconditional Stability and occasional Quiescent Current

I believe that’s my brief introduction about LDO. Hope it can benefit. =)
For that readers of the publish, please correct me if I am wrong.
Many thanks! =)

asicpark stated: seventh March 2008 17:54