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Fractional n frequency synthesizer thesis proposal

800-1600 MHz Synthesizer

Underneath CPLD Pinout

Exactly what is a fractional-N synthesizer?

The minimum step size an integer-N synthesizer equals the reference frequency (fREF ). Fractional-N synthesizers break this coupling the steps can be quite small indeed. Designers can increase comparison frequency and widen loop bandwidth – lock time is thus reduced refererence spurs and microphonics are eliminated. Fractional spurs, however, really are a new hazard.

Fractional-N synthesizers work by periodically altering the division ratio from N to N+1 and back so that the typical is N + F/M where ≤FM N,F and M are integers. For instance, if N is 5 for 99 cycles and 6 for just one cycle, 5.01 may be the average division ratio. A connected frequency counter would read 5.01 occasions fREF.

Regrettably, there is a catch: switching the division ratio seriously disturbs the PLL producing a sawtooth-like waveform around the VCO control line and severe FM sidebands around the output. Fortunately, the disturbance is foreseeable – as well as other means happen to be devised to cancel it.

Fractional-N synthesizers first made an appearance within the late 1960s and early 1970s. The first compensation schemes applied analogue correction towards the VCO control line. A notable design was the synthesizer by Nigel King for that RACAL RA1792 communications receiver. A breakthrough arrived 1984 when John Wells of Marconi Instruments invented a completely digital plan in line with the principle of noise shaping.

Noise shaping concentrates the quantisation noise created in the PFD output in to the greater frequencies where it’s removed through the low-pass filter. The loop structure is proven opposite.

The divider is controlled by a kind of sigma delta modulator referred to as a MASH.

Fractional n frequency synthesizer thesis proposal not large in bytes but

The division ratio N+ΔN isn’t limited to N and N+1, this will depend on the amount of stages (order) from the MASH.

MASH output, ΔN, is really a pseudo-random sequence. The VCO frequency is controlled by the lengthy-term mean of ΔN that is exactly F/M. Check out my MASH Theory Page for any mathematical treatment.

The MASH structure is a number of first-order sigma delta modulators, each given through the quantisation error from the previous stage. ΣΔ modulators are broadly utilized in A/D and D/A conversion, to attain high res from fast low resolution (e.g. 1-bit) converters by oversampling. The ΣΔ modulator is adopted with a low pass filter. Easily, inside aOrDeb applications, it is a digital filter. A really readable retrospective on ΣΔ modulators are available in chapter 3 of Ushaw [2].

Project objectives

Getting built a PLL for ethernet clock recovery. where acquisition speed not output wholesomeness was important, I needed to create a synthesizer having a clean output I needed to make use of exactly the same diode switching technique within the charge pump as RACAL utilized in the RA1792 – since i think it is a neat circuit and, I needed to utilize a CPLD (Complex Programmable Logic Device). This project scratched the 3 itches.

My original plan was to utilize a Motorola MC145152 PLL controlled with a CPLD, however when I stumbled upon this short article by Oleg Skydan, I realized I possibly could implement the divider and phase frequency detector (PFD) within the CPLD.

Fractional n frequency synthesizer thesis proposal 25 turns

This simplified the hardware and offered the chance to test different PFD designs.

The VCO center-frequency wasn’t important – it is really an experimental design – I selected a minimal frequency to simplify construction. The VCO tuning range was stored low (100 KHz) to lessen the result of noise around the VCO control line.


Altera EPM7160SLC84-10 (160 macrocells)

-70 dBc @ 50 Hz (United kingdom power line)

PFD Linearity

The traditional dual D-type switch-flop adopted by charge pump can exhibit dead-band. This can be a zone around Φ= in the center of the transfer characteristic in which the gain kPD falls to zero. It resembles crossover distortion and is because the charge pump transistors not switching on prior to the switch-flops are removed. This may lead to elevated close-in phase noise (jitter) since the loop simply reduces at really small phase errors. Delaying the PFD reset helps to ensure that both charge pumps are fully started up (before they turn off).

ΣΔ modulation creates high-frequency energy in the PFD output. Any non-linearity within the PFD can produce low frequency IMD products which aren’t removed through the LPF. Dead-band is a kind of non-linearity. Imbalance between source and sink currents within the charge pump is yet another.

Mr Skydan implemented an AD9901 style ultra-straight line dead-band-free detector. This divides the PFD inputs by 2 and compares them utilizing an XOR gate forcing the divided signals into quadrature. It’s perfectly straight line around Φ= because there’s no crossover. I made the decision to help keep this in reserve and check out a standard PFD with delayed reset first since i was rather wedded to my diode switching charge pump. I made use of an AD9901 style PFD within my 15-25 MHz Fractional-N Synthesizer.

CPLD Programming

I made use of Altera’s excellent Quartus II Web Edition 4.1 development software that is offered by world wide web.altera.com free of charge. Logic could be defined in Verilog or VHDL, however i mostly used the block editor which enables you to definitely draw a schematic. This can be a top-level module. The MASH is visible top playing N.F frequency command inputs. The Divisor[5..] output is N+ΔN:

The look is fully synchronous: VCO_Was global clock GCLK1. The divided VCO sload is introduced out as TEST_To illustrate multiplication of ΔN. DFF inst9 is essential because lpm_counter0 oscillates if cout is given straight to sload. With this particular extra DFF delay, because the countdown includes zero (e.g. 3,2,1,,3,1,2,. ), lpm_constant0 is really N-2.

The CPLD is programmed in-situ, through the PC parallel printer port, utilizing a ByteBlaster cable attached to the 10-way JTAG header.

Monster MASH

The EPM7160SLC84-10 CPLD has 160 macrocells that is sufficient for any fourth order 16-bit (modulus 65536) MASH. To really make it fit, I needed to update the accumulators sequentially (over 4 clock cycles) utilizing a shared 16-bit adder. Adders eat macrocells!

Here is a connect to a GIF picture of the Quartus block schematic from the fourth order MASH. It isn’t large in bytes but it’s in pixels and that’s why I’ve not inlined it.

Here’s an early on version. It may be worth searching only at that first because it is a bit simpler. Each accumulator has it’s own adder. Note, however, this version was clocked by sload .

Verilog code for calculating N+ΔN with sign-extension. This sub-module is baked into the MASH.

The Electricity bias current in the center of D2, D3 is placed roughly halfway between your everywhere logic levels using preset VR1. Once the switch-flops are removed, D1 and D4 conduct, D2 and D3 are reverse-biased. An increasing advantage on Lower_OUT shuts-off D1, D2 conducts, and .5mA flows in to the integrator. A falling advantage on UP_OUT switches another diode pair and .5mA flows from the integrator.

PFD reset is removed-nick (via R5) therefore incurring a CPLD I/O delay. The 70 pF trimmer can there be look around the aftereffect of modifying the delay. Close-in phase noise is noticeably reduced once the trimmer is fully meshed. The resultant delay is all about 30 ns.

Discrete 1 KHz spurs around a 4353 KHz carrier (N=17, F=0x0100) were reduced by growing C7 from 1n to 10n. The Fir KHz modulation (clearly visible around the VCO control line) could then be nulled-out by modifying VR1. The setting was quite critical. After carrying this out was the result from the trimmer noticeable.

R4/C7 give a pole at 720 KHz to pre-filter fast edges before they achieve the integrator op-amp with a gain-bandwidth product of just 10 MHz. Perhaps, C7 might be elevated further. Alternatively, although I’ve not attempted this, a passive loop filter may be safer, adopted with a low frequency op-amp gain buffer. Within the RA1792, RACAL used 22Ω / 100 pF and also the AD518 op-amp that also includes a GBW 0f 10 MHz!


The VCO is housed inside a diecast aluminium box with feedthru capacitors for power and tuning. L1 is 25 turns of No. 22 SWG enameled copper wire on the T68-6 powdered-iron toroid. Ferrite may have been a better option only at that frequency since L1 is responsive to magnetic fields. Waving a magnetised screwdriver around outdoors this area includes a pronounced impact on the inductance of L1.

I selected a sizable value for FET biasing resistor R9 to create pinch-from the amplitude restricting mechanism. I stored C9 no more than easy to minimise loading around the tuned circuit.

VCO Isolation Buffer (2 of)

There’s two identical isolation amplifers with SMA outputs at opposite ends from the VCO box. The output is not sinusoidal since a current oscillator tweak bending the amplitude! I added a 50Ω series resistor to prevent the emitter supporters hard-restricting, however the MOSFETs continue to be soft-restricting. Harmonics are, a minimum of, a great deal simpler to get rid of than phase noise!

The emitter follower are operating in class A. The quiescent current should be sufficient to provide the height load current.

Differential Limiter

This circuit, obtained from Rohde [1] (p239), converts the sine(ant) wave in the VCO right into a 5V square wave in the CPLD clock input.



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