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Ring oscillator design thesis proposal

Ring oscillator design thesis proposal flip-flop is reversed when

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Printed: 23, March 2015


A style of 93.31 MHz frequency generator according to CMOS gate ring oscillator is implemented, which could achieve a precision degree of 100 Hz. The look is simulated with LTspice. The attached parameters from the devices within the library are measured and sorted to get the best solution. The ultimate circuit is principally was comprised of XOR2 gates. The performance from the design is tested. The typical power consumption is .91mW. The increasing time, the falling time, and also the duty ratio from the design are relatively good.

Index Terms

CMOSFET oscillators, power consumption, propagation delay


THE ring oscillators, because of the inexpensive and small size, are broadly utilized in phase-locked-loops (PLL) for clock and knowledge recovery, frequency synthesis, clock synchronization in microprocessors, and lots of applications which require multi-phase sampling [1].

Ring oscillator design thesis proposal flip-flop in

Within the above applications, the time signals with relatively precise frequency might be generated by ring oscillators. Out of the box proven in Fig. 1, ring oscillator is was comprised of a strange quantity of inverting gates that are connected inside a ring or perhaps a closed loop. The regularity of the ring oscillator is roughly calculated by where f may be the frequency from the oscillator, Tp may be the propagation delay of every gate within the feedback loop, N is the amount of gates within the closed loop. Because each gate should change value two times to create one clock cycle, f is split by two. Used, not just the propagation delay of every gate plays a role in the time from the clock signal, but additionally another factors, for example capacitance, source current and how big the gates [2] [3].


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Within this paper, the ring oscillator is implemented with CMOS technology, that has relatively low static power dissipation, low output drive current and noise margin [4]. The propagation delay of CMOS gates, is required to create the time signal within the ring oscillator. The regularity from the frequency generator is 93.31MHz, having a precision of 100Hz. The gates within the library are tested and examined in Section II to find the best gate with this design. In Section III a strategy for applying the actual frequency is introduced.

The paper is concluded in Section IV.

II. Preliminary Frequency Approach

The objective of these studies is to acquire a clock signal having a frequency of 93.31 MHz which needs to be as precise as you possibly can. The look is dependant on LTspice, that is a high end circuit simulator. The provided gate library includes buffer, inverter, multiplex, nand2, nand3, nand4, nor2, nor3, nor4, xnor2 and xor2.

A. Frequency Conversion with D switch-flop

The first circuit diagram is proven in Fig. 2. The inverting gate chain includes a NAND2 gate and 4 inverters. Current source ‘V1′ supplies 3.3V Electricity power and ‘V2′ offers a step current being an excitation. A D switch-flop is required prior to the output signal whose output ‘QN’ is attached to the input D.

The output frequency of the circuit is all about 680MHz, that is far bigger compared to expected value. The D switch-flop within this circuit can be used for frequency division and rectification. The creation of the D switch-flop is reversed whenever a rising fringe of the time signal is detected. Thus, the regularity from the output signal of D switch-flop is 1 / 2 of the regularity from the clock signal. Therefore, with n D switch-flops the regularity might be divided by 2n. In addition, the job ratio might be modified to 50% through the D switch-flop.

In the description above, it is easy to attract a conclusion that D switch-flop is easily the most efficient device to lower the regularity of the oscillator. By connecting another two D switch-flop, as proven in Fig. 3, the output frequency could achieve to 175MHz.

B. Performance Tests from the Gates

As introduced in part one, the regularity could be based upon the gates within the closed loop. More particularly, the propagation delay of every gate plays a role in the time from the ring oscillator. Around the one hands, adding gates towards the closed loop can help to eliminate the regularity from the ring oscillator. However, for any ring oscillator with similar quantity of gates within the closed loop, replace a gate with a different one with a greater propagation delay may also lessen the frequency. The second approach is frequently accustomed to slightly alter the total frequency once the propagation delay of these two gates isn’t very different.


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To obtain the general qualities of every gate, an easy circuit, as proven in Fig. 4, is introduced to be able to control the variables. Throughout the test, the inverter is going to be substituted with different gates to determine the delay and power consumption individually. The current source “V2” supplies a square signal having a frequency of 100MHz (While testing the D switch-flop, the regularity supplied by “V2” is going to be 200MHz because of frequency division).

The calculating answers are indexed by Table I. The outcomes are measured in a perfect condition, which can be not the same as the sensible circuit. To ensure the validity from the data, a far more practical circuit is introduced. As proven in Fig. 5, four inverters are added in to the closed loop. With this particular circuit a frequency of 103MHz is achieved. By inserting the gate in to the closed loop, the regularity will disappear.

As pointed out above, the inverting gates within the closed loop ought to be odd. Therefore, while testing a gate, another inverter can be used to guarantee the ring oscillator works correctly (buffer doesn’t need this inverter). The testing outcomes of this circuit are indexed by Table II.

C. Discussions from the Preliminary Approach

Inside a gate that contains more amounts of transistors, a logic signal has to feed more amounts of transistors to accomplish a logic operation. Thus, a logic signal takes extended period to visit in the input towards the output. In this manner, a gate contains more amounts of transistors includes a longer rising and falling time.

Fig. 6 shows 2 kinds of CMOS gates that contains four transistors. The gate in Fig. 6 (a) only has one degree of transistors whereas that in Fig. 6 (b) has two amounts of transistors. Assume the transistors within the gates are similar. The signal within the second gate will need to take two times the switching duration of the transistor to feed.

The information in Table I’ve been sorted by propagation delay within the order in the tiniest towards the largest. In the table we are able to conclude the propagation delay from the top 5 gates is bigger than 10ns. However, D switch-flop couldn’t be utilized within the closed loop since the falling edge, which needs to be given back, is going to be filtered out by D switch-flop. Evaluating with XNR2 and XOR2, multiplexer and buffer consume more power. Within the real circuit, greater power consumption means more heat generation, which needs to be reduced whenever possible [5]. Within this situation, XNR2 or XOR2 ought to be utilized in the closed loop to be able to get yourself a better performance.

Evaluating the 2 tables, it’s not difficult to find the practical situation matches the person test of every gate above. Slight changes happen only between gates that have similar propagation delays. Observe that the ability consumption values in Table II are not only seen based on the gate that we’re investigating, but the other devises within the whole circuit. A circuit may consume more power once the frequency in greater [6]. Consequently, the ability consumption values in Table II can’t be considered because the look at actual performance from the gates.

To lessen the ability consumption, all of the inverting gates within the closed loop is going to be substituted with XOR2 except the first NAND2 gate. Two D switch-flops may also be removed departing just one D switch-flop to rectify the present.

III. Precise Adjustment

There’s two avoidable factors influencing the truth of simulation leads to these studies. First of all, like a circuit simulator, the simulation results could change slightly once the simulation settings are altered. Next, the ring oscillator needs several periods from the beginning from the simulation to stabilize the output frequency. To help make the result stable, the simulation period is bound to 300ns and also the waveforms between your eighth rising edge and also the eighteenth are measured. For the simulations throughout the research, same simulation settings are employed.

Having a closed loop that contains 14 XOR2 gates, the output frequency can achieve 104MHz. However, with 16 XOR2 gates within the closed loop, the output frequency is 90MHz, that is a little smaller sized compared to target value. Therefore, a brand new method ought to be brought to precisely adjust the regularity.

A. Modifying the regularity with Capacitances

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