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Floating point multiplier thesis proposal

Floating point multiplier thesis proposal The Vedic Mathematics

Pratiksha Rai. Shailendra Kumar. Prof. (Dr.) S.H.Saeed. “Style of Floating Point Multiplier Using Vedic Aphorisms”, Worldwide Journal of Engineering Trends and Technology (IJETT), V11(3),123-126 May 2014. ISSN:2231-5381. world wide web.ijettjournal.org. printed by seventh sense research group

The term ‘Vedic’ is obtained from the term ‘Veda’ i.e. the shop-house of understanding. Mathematics, produced from the Veda provides one line, very fast and mental methods together with quick mix checking systems. The Vedic mathematics was rediscovered in early last century from ancient Indian sculptures (Vedas). What we should call VEDIC MATHEMATICS is really a mathematical elaboration of ‘Sixteen Simple Mathematical formulae in the Vedas’ as introduced out by Sri Bharati Krishna Tirthaji. Vedic Multiplication Technique will be employed to implement Floating point multiplier. For mantissa multiplication I’m using Urdhva-Tiryagbhyam sutra. The underflow and also over flow cases is going to be handled. The inputs towards the multiplier in 32 bit IEEE 754 format. Within this paper, I suggested the style of high-speed Vedic Multiplier while using techniques of Ancient Indian Vedic Mathematics which have been modified to enhance performance. Vedic Multiplication Strategy is accustomed to implement IEEE 754 Floating point multiplier. For mantissa multiplication I’m using Urdhva-triyakbhyam sutra for that underflow and also over flow cases are handled. The multiplier’s inputs are supplied in IEEE 754, 32 bit format. The Vedic Mathematics may be the ancient system of mathematics with a unique manner of calculations according to 16 Sutras. My work has demonstrated the efficiency of Urdhva-Tiryagbhyam, Vedic way of multiplication which strikes a positive change in the procedure for multiplication.

Floating point multiplier thesis proposal MULTIPLIER USING

It enables parallel generation of intermediate products, eliminates undesirable multiplication steps with zeros and scaled to greater bit levels using Karatsuba formula using the compatibility to various data types. The Urdhva-Tiryagbhyam Sutra is most effective Sutra (Formula), giving minimum delay for multiplication of all of figures, either big or small. I implement this multiplier using VHDL. I implement my work by Xilinx ISE tool i.e. accountable for synthesis also. For simulation I’m using Modelsim 10.2a.

[1] Booth, A.D. “A signed binary multiplication technique,” Quarterly Journal of Mechanics and Applied Mathematics, vol. 4, pt. 2, pp. 236– 240, 1951.
[2] Jagadguru Swami Sri Bharath, Krsna Tirathji, “Vedic Mathematics or 16 Simple Sutras In The Vedas”, Motilal Banarsidas, Varanasi (India),1986.
[3] Shripad Kulkarni, “Discrete Fourier Transform (DFT) by utilizing Vedic Mathematics”Papers on implementation of DSP algorithms/VLSI structures using Vedic Mathematics, 2006, world wide web.edaindia.com, IC Design portal.
[4] IEEE 754-2008, IEEE Standard for Floating-Point Arithmetic, 2008.
[5] Tariquzzaman et al,“ FPGA implementation of 64 bit RISC processor with Vedic multiplier using VHDL” IOSR Journal of Electrical and Electronics Engineering (IOSR-JEEE) e-ISSN: 2278-1676, p-ISSN: 2320-3331 PP 12-16.
[6] BHAGYASHREE HARDIYA et al “IMPLEMENTATION OF FLOATING POINT MULTIPLIER USING VHDL” Technology and Engineering (BEST: IJMITE) Vol. 1, Issue 3, 12 , 2013, 199-204 BEST Journals.

Floating point multiplier thesis proposal provides one line, super fast

Vedic Mathematics, VHDL, Urdhva-Tiryagbhyam Sutra.

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