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Capacitor less ldo thesis proposal

Capacitor less ldo thesis proposal are able to describe the

Capless LDO design

  • Ronk 2013 slo V Capacitor-less Straight line Regulator with NMOS Power Transistor V. Molata1, 2, V. Kote1, 2, J. Jakovenko1 1 Department of Microelectronics, Faculty of Electrical Engineering, CTU in Prague, Technicka 2, Prague 2 ST-Microelectronics s.r.o. Pobrezni 620/3, Prague E-mail: molatvla@fel.cvut.cz, kotevlas@fel.cvut.cz, jakovenk@fel.cvut.cz Abstract: A 3.6 (4.3) V 50 mA capacitor-less straight line current regulator for system on nick (SoC) is introduced. It doesn’t require any exterior component that is stable in many of load current. This regulator uses an NMOS transistor because the power element. To be able to enhance the gate current within the power element switched floating capacitor can be utilized. The suggested straight line regulator remains created in an industrial .13 µm CMOS technology. The variation of output current is under 100 mV even when a whole load step may be used and current usage of this regulator is 150 µA whatever the load current. INTRODUCTION While using the growing effort to integrate all circuits in a single nick, therefore creating a SoC solution, the requirements for power management unit (PMU) that is integration are increasing [1]. Ideally, each block within the SoC must be provided by independent controlled current. You can do this employing a dedicated on-nick straight line current regulator for every circuit within the SoC. The primary assumptions which are made on regulators within the SoC are small plastic area, low power dissipation, and finally having less exterior components that has got to easily be attached to the nick, thus growing the cost within the whole system and occupy pins of nick itself. Straight line regulators may be separated into two fundamental groups [2]: • Conventional straight line regulators • LDO (low drop-out) regulators The only real of these two topologies, reaches orientation in the power transistor. Conventional straight line regulator uses transistor that’s linked to keep drain, or that particular transistor is substituted getting a bipolar transistor (BJT), or two transistors in Darlington configuration. Within the contrary LDO regulator uses configuration with common source. These two fundamental configurations are portrayed within the Fig. 1. Really the only orientation in the power transistor includes a general effect on both working mode and stability within the straight line regulator. The key element that has the very best effect on transient response within the regulator may be the power transistor. This transistor delivers needed current towards the load impedance which leads to needed output current. A delay that’s because the ability transistor within the control loop is caused because gate capacitance in the power transistor represents current current ripping tools. The higher gate capacitance, the higher may be the delay. This delay has dominant role within the entire delay within the control loop. In LDO regulators a PMOS transistor (Fig. 1) enables you to keep source configuration as being a power element. Though this configuration several disadvantages occur. The first trouble with using PMOS transistor is its lower mobility compared to NMOS transistor. Meaning PMOS transistor needs bigger plastic area than NMOS transistor for comparable characteristics [3]. This bigger power transistor reduces rate of charging common source. This configuration has greater output impedance in comparison with source follower configuration within the NMOS Fig. 1: Topologies of straight line regulators.
  • regulator (Fig. 1). For LDO regulators this adds another low-frequency pole whose frequency depends both on load resistance and output capacitance. To make sure stability a large exterior capacitor along with other compensation circuit is required. Another drawbacks connected while using the low frequency dominant pole are bandwidth limitation along with the slow load regulation response. This can be frequently enhanced by fast loops that increase regulator bandwidth [4]. Each one of these disadvantages connected while using the PMOS transistor may be eliminated while using the NMOS transistor. This power transistor is connected within the configuration referred to as source follower. An essential symbol of this circuit is low output impedance, meaning the output pole lies in the high frequency. Being conscious of the we don’t make use of the output pole as dominant pole and so we don’t need exterior capacitor. Additionally, since the NMOS transistor has greater mobility, for the same output current a considerably smaller sized sized sized part of plastic is needed. However, despite NMOS power transistor several disadvantages are connected. One of the greatest drawbacks may be the gate current of power transistor needs to be no under by Vgssat more than the output current. This itself isn’t an issue, but in addition while using the ever decreasing supply current, this leads the supply current could possibly get below possible quantity of gate current. Consequently the ability transistor requires charge pump. An alternative to raise the gate current is approach referred to as gate overdrive [5], which uses floating current supply to improve the control current in a range sufficient to help keep the NMOS pass element operating in saturation region. CAPACITOR-LESS Straight line/LDO REGULATORS Conventional straight line/LDO regulators come in common use and they’re still being developed [6] and [7]. However a substantial a part of current research of regulators targets capacitor-less straight line/LDO regulators [8], [9] and [10]. By removing an exterior capacitor within the regulator we introduce new Fig. 2: Simplified circuit diagram for capacitor-less LDO regulator. options in power management like decrease in nick area, less pins are very important and this leads to insufficient the cost within the whole system. Across the Fig. 2 you are able to understand that there’s still a capacitor within the growth and development of a capacitor-less LDO regulator. But unlike straight line regulators (Fig. 1) (in which the output capacitor is inside the selection of several microfarads) the requirement of this internal capacitor for capacitor-less LDO regulators will always be smaller sized sized sized (out of all different several hundreds picofarads) and so its transient characteristics are often worse. For this reason you have to apply enhancement structure to improve transient response. Characteristics of Transient Responses Existence of a huge exterior capacitor at conventional straight line/LDO regulators generally improves characteristics within the regulator during transient responses. It’s because of the fact the output capacitor stores energy is proportional for that output current. This energy is altered into current during changes. Once we stood a perfect capacitor with infinite bandwidth and nil internal resistance, then, this sort of capacitor would react immediately. During alteration of the charge from capacitor for that load a small little bit of output current is produced. Equation 1 roughly describes relation between drop of current Vout, charge Q and cost within the capacitor Cout. As you can noticed in the equation 1, change of output current is inversely proportional to the requirement of the outdoors capacitor. Transient characteristics of Fig. 3: Conventional LDO regulator with reduced loop bandwidth that is equivalent circuit diagram for fast load transients [10].
  • out out C QV (1) a regulator may be improved by growing the requirement of this exterior capacitor. When the load transients are often quicker than time response within the regulator, that’s normal with growing clock frequency of IC, then concept of the equation 1 is a lot more apparent. Fig. 3 depicts this case for conventional LDO regulator. When the time response within the regulator will always be smaller sized sized sized than load transients we’re able to suppose constant gate current along with the power transistor consequently may be substituted with constant current source. By using this on mind the progres within the output current is described directly by equation 1. Unlike conventional straight line/LDO regulators, capacitor-less straight line/LDO regulator misses large exterior capacitor and so its transient characteristics are often worse. To improve these traits you have to exchange constant current source from Fig. 3, in which the power transistor is proven, by an adaptive method of getting current, that may react on fast changes of loading current. Kind of a Capacitor-less Straight line Regulator The goal of the task should be to design a capacitor-less straight line regulator for SoC applications. It’s important for the circuit to obtain stable whatsoever loading currents, mainly during small loading currents. Also, it’s important the circuit has acceptable reactions on fast change of load. By using this reason you have to raise the circuit by fast loops, that accounts for fast response within the circuit that will have greater bandwidth in comparison with slow controlling loop. You have to include these circuits because of inadequate an exterior loading capacitor. The fundamental idea of the designed circuit is portrayed within the Fig. 4. Within the concept you can check out a quick loop, that improves transient parameters within the circuit, additionally to slow loop is proven. This slow loop sets the right output current with the steady condition or during slow vary from the loading current. However, rapid loop should react across the fast transient changes of loading current and so to deal with adjustments to output current. Also, low Fig. 4: Fundamental idea of capacitor-less straight line regulator with NMOS power transistor. technique entire regulator belongs into aims in the work. It’s from why increasingly more more emphasis is laid on efficiency in power management. Idea Of NMOS CAPACITOR- LESS Straight line REGULATOR Within the following part we’ll describe core within the circuit (Fig. 5) and implementation of enhancement structure (Fig. 6), that’s frequently useful for realization within the NMOS capacitor-less straight line regulator. Foundation the circuit may be the power transistor (MPT) similarly because the topology of classic straight line regulator. This type of regulator is comparable to a present source which will keep output current constant and outdoors of difference in load or change of battery current. Current IPT, that’s controlled by gate current across the MPT, is split relating to the load within the regulator along with the transistor M5, as portrayed within the Fig. 5. Fig. 5: The main within the NMOS capacitor-less straight line regulator. Current source I8 delivers constant current, charging the gate capacitance within the power transistor. Transistor M5 similarly such as the power transistor MPT, works in saturating mode along with a control current from slow loop (VDCloop) may be used for the gate. The present I5, flowing through this transistor depends on the current Vgs5 (Vgs5 = VDCloop – Vout) and for that reason we’re able to condition it truely does work just like a comparator. Magnitude in the present, which flows from current source I2, is constant plus steady condition provided by a few currents I5 and I8, as portrayed within the Fig. 5. After general introduction of fundamental elements within the circuit we’re able to describe the key factor which this straight line regulator creates. Very similar as it is at fundamental topology of regulator, even here a loop of feedback closes via comparator. The feedback enables you to make the output current. Adjustment draws on the very fact current from source I2 is constant, along with the vary from the current I5 causes vary from the current Ic/d, affecting amount of charge across the gate of power transistor and related gate current across the power transistor. Because it was stated earlier,
  • Fig. 6: Circuit implementation within the capacitor-less straight line regulator with NMOS power transistor. transistor M5 regulates the quantity of current I5 which is dependent upon the progres of load. As it is apparent inside the equation 2, output current within the regulator, Vout, depends only on constants as well as on the present I5. ox 5 5 5 trefout 2)( C L W IVVV µ = (2) Inside the modification of load, the present source I8 still delivers constant current, meaning, that gate current within the power transistor V0 is controlled by change of current Ic/d. Thus the present which flows while using power transistor is controlled using the current I2, resp. using the current I5 therefore closing feedback. The truly amazing factor concerning this circuit is its speed because of the fact the circuit works in the present mode. Concurrently the circuit has one dominant disadvantage – great stand-by current consumption for acceptable transient response. Maximum charging speed within the input gate capacitance within the power transistor is bound by current source I8. The magnitude in the present, that’s delivered using this source, is generally half in the I2 current. For the reason that charging/discharging within the power transistor gate should have similar maximum speed. As proven in Fig. 4, NMOS capacitor-less straight line regulator includes error amplifier, floating current source, power transistor, compensation systems along with the feedback network. The output current within the error amplifier (Vctrl) is elevated inside the supply level getting a continuing floating current source. Theoretically the floating current source might be implemented as being a billed floating capacitor. However, the current inside the capacitor would drop because of its leakage current. This issue is solved by using two switched floating capacitors. Implementation of Capacitor-less Straight line Regulator Idea of straight line regulator, which had become the final part, ought to be rearranged in other to obtain recognized in integrated form and also to improve its parameters like current consumption. Which are more fundamental changes belongs adding differential amplifier, which maintains needed operation reason for the entire regulator. Also, we added cascade transistor M6. Furthermore, we added capacitive differentiator (Cf, Rf, M10, M11) [9] and [10], which compensates transient response, and lastly a discharge transistor M7 [5]. Fig. 6 depicts the elementary parts that are mentioned. With the aid of differential amplifier into the idea of regulator is produced series connection of two feedback loops. The final loop, portrayed within the Fig. 5, represents series fast loop since the differential amplifier creates slow loop. For improvement of PSRR (Power Rejection Ratio) within the circuits can be utilized simple to provide differential amplifier from the introduction of regulator. Subliminal mode within the power transistor considerably slows lower the response within the circuit. This may cause degradation in current regulation for applications where loading currents drop to really ‘abnormal’ amounts in a short time. This degradation in transient response of regulator may be eliminated with the aid of a discharge circuit. This is often another arrangement of circuits within the regulator that will improve transient response within the regulator during fast insufficient loading current. Fig. 6 depicts principal connection within the regulator along with discharge transistor. This discharge circuit works only when controlling loop doesn’t be employed in keeping mode but it’s in saturation (during extremely fast changes of loading currents).
  • RESULTS AND COMPARISON The suggested straight line regulator was created within the .13 µm CMOS technology. It provides a controlled growth and development of 3.6 V or 4.3 V. The regulator was created for delivering the perfect output current of fifty mA getting the very least drop-from 100 mV. The ability transistor includes a W/L (width/length) ratio much like 4000 µm/.5 µm. Probably the most quiescent current within the regulator is 150 µA, which inserts under .5% within the maximum load current. The duty regulation response within the regulator is tested by switching the duty current from 100 µA to 10 mA and the opposite way round with trise/tfall edge 1 µs (Fig. 7) resp. 10 ns (Fig. 8). Maximum output current variation for typical issues that was acquired inside the simulation for NMOS capacitor-less straight line regulator is all about 76 mV (Fig. 7(a)) as well as for PMOS capacitor-less LDO regulator is all about 41 mV (Fig. 7(b)). You are able to understand that for edge 1 µs PMOS capacitor-less LDO regulator has better results (variation of output current is nearly two occasions smaller sized sized sized than NMOS capacitor-less straight line regulator). Opposite situation exist in the problem when trise/tfall edge becomes manifest pretty quickly (10 ns). Variation of output current for PMOS capacitor-less LDO regulator (Fig. 8(b)) is all about 210 mV greater in comparison with NMOS capacitor-less straight line regulator (Fig. 8(a)). Table 1 summarizes the performance within the suggested NMOS capacitor-less straight line regulator in comparison to PMOS capacitor-less LDO formerly reported [11]. As you can seen, the current work presents greater maximum output current (50 mA), through getting a much better dynamic performance for fast variation of load current, what this means is a quicker setting serious amounts of somewhat variation within the output current. CONCLUSIONS New NMOS capacitor-less straight line current regulator was introduced, which is capable of doing delivering 3.6 V or 4.3 V at loading currents around 50 mA. PMOS capacitor-less LDO regulator [11] has two occasions lower current consumption in comparison with suggested regulator but however maximum current load elevated five occasions greater than PMOS capacitor- less LDO regulator [11]. NMOS capacitor-less straight line current regulator doesn’t need any exterior component that is stable within the wide load current range with capacitive bunch to two nF. Extensive simulation results demonstrate the functionality within the design. ACKNOWLEDGMENTS The task is among the CTU SGS grant No. SGS11/156/OHK3/3T/13. (a) NMOS capacitor-less straight line regulator (b) PMOS capacitor-less LDO regulator [11] Fig. 7: Comparison of transient response across the load step from 100 µA to 10mA with trise resp. tfall 1 µs. (a) NMOS capacitor-less straight line regulator (b) PMOS capacitor-less LDO regulator [11] Fig. 8: Comparison of transient response across the load step from 100 µA to 10mA with trise resp. tfall 1 µs.
  • Table 1: Comparison of results between suggested NMOS capacitor-less straight line regulator and PMOS capacitor-less LDO regulator [11]. Suggested NMOS straight line regulator PMOS LDO Simulation Simulation Parameter Name Test conditions Min Typ Max Min Typ Max Unit Input supply current Vplus (Vplus) (Vgnd) 3.77 4.8 5.5 3.77 4.8 5.5 V Output current Iload 50 10 mA Output current Vout VSEL = `0` VSEL = `1` 3.587 4.283 3.6 4.3 3.621 4.324 3.583 4.276 3.6 4.3 3.626 4.334 V Expected parasitic load Cout ESR .1 2 250 .1 5 250 nF m Current consumption Idd Iload = 10 mA Iload = 100 µA 100 100 135 142 65 58 72 67 µA Load transient Ldtr Iload @ trise (tfall) = 1 µs from 100 µA to 10 mA from 10 mA to 100 µA 30°C to 125°C 76 16 97 27 41 27 72 47 mV Iload @ trise (tfall) = 10 ns from 100 µA to 10 mA from 10 mA to 100 µA 30°C to 125°C 280 107 547 297 591 71 890 186 REFERENCES [1] H. Eul, “ICs for mobile multimedia communications,” IEEE Worldwide Solid- Condition Circuits Conference, pp. 21–39, 2006. [2] C. Simpson, „A user’s self-self-help guide to getting to pay for low-dropout regulators“, Wescon Conference, Santa Clara, pp. 270-275, November. 1997. [3] W. Kruiskamp, R. Beumer, “Low drop-out Current Regulator with Complete-nick Capacitance for Slot Based Operation,” ESSCIRC2008, 34th European Solid Condition Circuits Conference 2008, Edinburgh United kingdom, pp 346-349, Sept. 2008. [4] P. Hayucha, T. Karnik, B. Bloechel, C. Parsons, D. Finan, S. Borkar, “Area-efficient Straight line Regulator with Ultra-Fast Load Regulation,” IEEE Journal of Solid-Condition Circuits. Vol. 40, Issue 4, pp. 933-940, Apr. 2005. [5] V. Ivanov, “Design Methodology and Circuit Means of Any-Load Stable LDOs with Instant Load Regulation and periodic Noise,” Workshop on Advances on Analog Circuit Design 2008, Texas Instruments, Apr. 2008. [6] M. Al-Shyoukh, H. Lee, “A transient-enhanced low-quiescent current low-dropout regulator with buffer impedance attenuation,” IEEE Journal of Solid-Condition Circuits, vol. 42, pp. 1732–1742, 2007. [7] T. Y. Man, PKay. T. Mok, “A larger slew-rate push– pull output amplifier for low-quiescent current low-dropout regulators with transient- response improvement,” IEEE Transactions on Circuits and Systems II, 9, pp. 755 –759, 2007. [8] L. Yat-Hei, K. Wing-Hung, T. CHI-YING, “Adaptively-biased capacitor-less CMOS low dropout regulator with electricity feedback,” Asia and South Off-shore Conference on Design Automation 2006, pp. 2, Jan. 2006. [9] R. J. Milliken, J. Silva-Martinez, E. Sanchez- Sinencio, “Complete-Nick CMOS Low-Dropout Current Regulator,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 9, pp.1 879-1890, Sept. 2007. [10] P. Y. Or, and K. N. Leung, “An output- capacitorless low-dropout regulator with dc-spike recognition,” IEEE Journal of Solid- Condition Circuits, vol. 45, no. 2, pp. 458-466, 2010. [11] V. Molata, “Kind of capacitor-less LDO regulator in CMOS technology,” Diploma thesis, ST-Ericsson and Czech Technical College in Prague – FEE, June 2011.

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